I. Field of the Invention
The present invention relates to an information transferring apparatus which has an improved data buffer disposed between an information processor unit and an input/output unit.
II. Description of the Prior Art
In the past it has been common for an information transferring apparatus, for example as shown in FIG. 1, to include a first-in first-out (FIFO) stack 30 to perform as a data buffer between an information transferring unit 10 and an input/output unit 20. The number of words included in the FIFO stack (the depth of information) is determined by the components constituting the buffer, e.g., the number of storage locations included in a physical memory and cannot be altered by a program. Such an arrangement is not problematic when the input/output unit is of the type in which the direction of information flow is unidirectional, such as from the information processing unit to a printer, paper tape punch, or a display. This is because in such devices once the information has been transferred to the first location of the FIFO stack it will be unavailable to the input/output unit until the information has been shifted through the series of data storage locations or memory elements constituting the FIFO stack. However, in the situation where status information or command information is stored in the FIFO stack, it is often the case that the information most recently entered into the FIFO stack 30 will be required to be processed by the information processing unit.
The FIFO stack 30 is formed of a plurality of memory elements connected in series wherein information words, e.g., data words, status data, and control information, stored in the first stage memory element of the FIFO are rippled through subsequent memory elements as it is shifted to the last stage memory element. From the last stage memory element the information is next shifted to some other system element such as an I/O controller or a peripheral device. Accordingly, in a case where the central processing unit 10 must check the information most recently stored in the FIFO stack 30, it is impossible to instantly read the newest information from the FIFO stack 30. That is, information requested by the central processing unit 10 must first be shifted to the last stage memory element of the FIFO stack 30, must then be transferred from the FIFO stack 30 to the input/output unit 20, and finally must be transferred to the central processing unit 10. This necessitates a highly complex circuit and is very time-consuming.